A data-driven map of China's 2024–2026 AI semiconductor landscape: who is actually shipping, who is catching up, who is bluffing. Compiled from primary filings (SSE, SEHK), company annual reports, Reuters, Bloomberg, SCMP, and the Bureau of Industry and Security Entity List.
China's AI semiconductor industry in 2026 is a paradox: simultaneously more successful and more constrained than anyone predicted in 2022. Huawei Ascend 910C-based clusters now train state-of-the-art Chinese foundation models end-to-end. Cambricon posted its first quarterly profit. Biren went public in Hong Kong on 2 January 2026. Moore Threads jumped 468% on its Shanghai debut in December 2025.
Yet the structural bottleneck is the same as it was in October 2022: high-bandwidth memory (HBM), leading-edge EUV lithography, and the software moat around CUDA. SMIC's multi-patterned DUV 7nm node works — but it's slow, expensive, and yield-constrained. CXMT and YMTC are climbing the curve but remain 2–3 generations behind Micron / Samsung / SK Hynix.
The near-term trajectory (2025–2027) is one of import-substitution at mid-performance tiers, not global leadership. Chinese chips will dominate Chinese data centres by regulatory fiat long before they win a single Western customer. The real contest is whether that captive market is large enough to fund the R&D pipeline required for long-term parity.
Our probability-weighted base case: Huawei Ascend reaches 75–80% of NVIDIA next-gen training performance by 2027 for Chinese-domestic workloads, with a 3–5× price gap internationally that limits exports. Cambricon and Biren split the #2 slot. Moore Threads remains a gaming/edge play. Hygon's x86 franchise hits a ceiling as domestic substitutes mature.
Opening salvo. HiSilicon cut off from TSMC <7nm fabrication by direct extension (2020 FDPR update). Kirin smartphone chip pipeline effectively halted for three years.
Blanket restriction on export of NVIDIA A100/H100 to China; 18nm DRAM, 128-layer NAND, and 14/16nm logic fab equipment controlled. Created the "A800/H800" workaround SKUs. The rule that created the modern Chinese AI chip industry.
BIS press releaseA800/H800/L40S banned. Performance-density and interconnect thresholds replaced raw FLOPS to prevent redesigned-down chips. Biren, Moore Threads, and 13 others added to Entity List. China's cloud GPU cluster plans set back 12–18 months.
BIS · Oct 2023 ruleHBM2e/HBM3 and downstream AI accelerators blacklisted. 140 additional Chinese entities added, including fab tool suppliers and CXMT-linked companies. The HBM ban is the single most damaging move — directly caps LLM training memory bandwidth for every Chinese player.
BIS · Dec 2024 ruleThailand and Malaysia brought into AI-chip diversion rules after reports of large NVIDIA H100/H200 volumes transshipping to China via third-party integrators.
Reuters reports China has completed a prototype EUV lithography machine in Shenzhen; first working chips expected 2028–2030. Timeline consistent with ASML's own initial NXE development curve (~5 years prototype-to-volume).
| Company | HQ | Founded | Flagship AI Chip | Node (nm) | vs H100 | Fab | Rev-24 ($M) | Listing | Sanction Status |
|---|---|---|---|---|---|---|---|---|---|
| Huawei HiSilicon Ascend line |
Shenzhen | 1991 | Ascend 910C | 7 | ~60% | SMIC N+2 | ~12,000 est. | Huawei (private) | ENTITY 2019 |
| Cambricon 寒武纪 |
Beijing | 2016 | MLU590 / Siyuan 590 | 7 | ~40–50% | TSMC 7 (legacy) / SMIC | ~165 | SSE 688256 | ENTITY 2022 |
| Biren Technology 壁仞 |
Shanghai | 2019 | BR100 / BR104 | 7 | ~50% (unsanctioned BR100) · derated post-2023 | TSMC 7 (pre-ban) | n/d | SEHK 6082 (IPO Jan-2026) | ENTITY 2023 |
| Moore Threads 摩尔线程 |
Beijing | 2020 | MTT S4000 (KUAE) | 12 | ~25–30% | TSMC 12 (legacy) / SMIC | ~70 | SSE 688795 (IPO Dec-2025) | ENTITY 2023 |
| Enflame (Suiyuan) 燧原 |
Shanghai | 2018 | CloudBlazer L600 | 12 | ~20–30% | GlobalFoundries/SMIC | n/d | Private · Tencent-backed | Monitored |
| Iluvatar CoreX 天数智芯 |
Shanghai | 2015 | Tiangai BI-V150 | 7 | ~20–30% | TSMC (legacy) | n/d | Private | Monitored |
| Hygon Info Tech 海光 |
Beijing/Tianjin | 2014 | DCU Z100 (HPC/AI) | 12/7 | ~30% (HPC-focused) | SMIC / TSMC legacy | ~830 (2023) | SSE 688041 | ENTITY 2019 |
| Horizon Robotics 地平线 |
Beijing | 2015 | Journey 6 (edge/ADAS) | 7 | N/A — edge AI only, 560 TOPS | TSMC / Samsung | ~330 | SEHK 9660 (Oct-2024 IPO) | Unsanctioned |
| Black Sesame 黑芝麻智能 |
Shanghai/Wuhan | 2016 | Huashan A2000 (autos) | 7 | N/A · 250 TOPS edge | TSMC | ~75 | SEHK 2533 (IPO Aug-2024) | Unsanctioned |
| Loongson 龙芯 |
Beijing | 2001 | 3A6000 / 3C6000 (LoongArch) | 14/12 | ~10% (HPC/CPU, AI secondary) | SMIC | ~70 | SSE 688047 | Unsanctioned |
| Zhaoxin 兆芯 |
Shanghai | 2013 | KaiXian KX-7000 (x86 CPU) | 16 | ~10% (CPU, not AI-first) | TSMC legacy / SMIC | ~140 est. | Private · VIA JV | Unsanctioned |
| UNISOC 紫光展锐 |
Shanghai | 2018 (spin) | T820 / S8000 SoC | 6 | N/A — mobile SoC w/ NPU | TSMC | ~2,100 est. | Private · Tsinghua Unigroup | Unsanctioned |
| Lisuan Tech 砺算 |
Shanghai | 2021 | G100 GPU (gaming + AI) | 6 | ~15% (early) | SMIC | pre-rev | Private | Unsanctioned |
| Vastai (瀚博) | Shanghai | 2018 | SV102 (inference) | 7 | ~25% inference | TSMC legacy | n/d | Private | Monitored |
| Baidu Kunlun | Beijing | 2011 (spun 2021) | Kunlun P800 (3rd gen) | 7 | ~50% BF16 inference | SMIC N+2 | internal | Subsidiary of Baidu | Unsanctioned (co.) |
| Alibaba T-Head 平头哥 |
Hangzhou | 2018 | Hanguang 800 / PPU | 12/7 | ~40% inference | TSMC / SMIC | internal | Alibaba subsidiary | Unsanctioned |
| MetaX (沐曦) | Shanghai | 2020 | MXC500 / Xi-Yun | 7 | ~30% training | TSMC 7 legacy | pre-rev | Private (IPO tutoring 2025) | Monitored |
| ByteDance (in-house) | Beijing | internal | Custom ASIC (2024 reports) | 7 | early | TSMC / SMIC | internal | ByteDance | Unsanctioned |
Performance estimates synthesised from SemiAnalysis, Tom's Hardware, HPCwire, Reuters, SCMP, and vendor specs. "vs H100" is effective real-world training throughput on LLM workloads (FP16/BF16 including memory-bandwidth effects), not peak TOPS. Entity List status: BIS.
| Company | HQ | Founded | Memory Segment | Leading Product | Node | Cap (Kwpm) | Global Share | Sanction |
|---|---|---|---|---|---|---|---|---|
| YMTC 长江存储 |
Wuhan | 2016 | 3D NAND | X3-9070 · 232L QLC (Xtacking 3.0) | 2x nm | ~100 | ~6% | ENTITY 2022 |
| CXMT (ChangXin) 长鑫存储 |
Hefei | 2016 | DRAM (DDR4/DDR5/LPDDR5) | DDR5-6400 · LPDDR5x 16Gb | 17 nm | ~240 (Q4-25) | ~10% target | Monitored · March 2024 rule |
| GigaDevice 兆易创新 |
Beijing | 2005 | NOR Flash · MCU · Niche DRAM | GD25 SPI NOR · GD5F NAND | 55/45 nm | fabless | ~20% NOR global | Unsanctioned |
| JHICC (Fujian Jinhua) | Jinjiang | 2016 | DRAM (niche) | 25nm DDR4 (recovered) | 25 nm | ~25 | <1% | ENTITY 2018 |
| Wuhan Xinxin (XMC) | Wuhan | 2006 | NOR / Niche | ZFlash / NOR | 65/45 nm | ~20 | ~2% NOR | Unsanctioned |
| Xi'an UniIC | Xi'an | 2015 | DRAM | DDR3/DDR4 niche | 2x nm | ~10 | <1% | Unsanctioned |
| CXMT HBM project | Hefei / Wuhan | 2024 (initiative) | HBM (HBM2/HBM2e target) | Pre-volume pilot line | TBD | pilot | 0% | Dec 2024 impact |
Every modern LLM trainer needs HBM3/HBM3e next to the logic die: H100 uses 80 GB HBM3 at 3.35 TB/s; H200 uses 141 GB HBM3e at 4.8 TB/s. Without equivalent memory, even a perfectly-matched logic die can't feed its tensor cores. China has no volume HBM producer as of 2026. SK Hynix, Samsung, and Micron supply 100% of global HBM. The December 2024 BIS rule was designed precisely to keep it that way until domestic CXMT-led HBM2e pilots mature (earliest 2026–2027).
CXMT's path runs through standard DDR5 → LPDDR5x → HBM2e stacking. YMTC's NAND is world-competitive on layer count (232-layer at Xtacking 3.0, matching Micron) but NAND doesn't replace HBM. The HBM gap, not the logic gap, is why China's best training clusters still rely on stockpiled NVIDIA silicon.
| Chip | Node | FP16 TFLOPS | Memory | BW TB/s | Interconnect | Software | TDP | Export Status |
|---|---|---|---|---|---|---|---|---|
| NVIDIA H100 SXM | 4N (TSMC) | 989 | 80GB HBM3 | 3.35 | NVLink 900 GB/s | CUDA + cuDNN + TRT | 700 | Banned to China |
| NVIDIA H20 (China SKU) | 4N | 148 | 96GB HBM3 | 4.0 | NVLink 900 GB/s | CUDA full | 400 | Further restricted 2025 |
| Huawei Ascend 910C | 7 (SMIC N+2) | ~800 (dual-die) | 128GB HBM2e (stockpile) | ~3.2 | HCCS 392 GB/s | CANN + MindSpore | ~400 | Entity |
| Huawei Ascend 910B | 7 | ~320 | 64GB HBM2e | ~1.6 | HCCS 200 GB/s | CANN + MindSpore | ~310 | Entity |
| Cambricon MLU590 | 7 | ~512 | 96GB HBM2e | ~2.4 | MLU-Link | BANG SDK / Neuware | ~350 | Entity 2022 |
| Biren BR100 | 7 (TSMC pre-ban) | ~1024 (vendor peak) | 64GB HBM2e | ~1.6 | BLink 192 GB/s | BIRENSUPA (emerging) | ~550 | Entity 2023 |
| Moore Threads MTT S4000 | 12 | ~100 | 48GB GDDR6 | ~0.77 | MTLink 240 GB/s | MUSA · CUDA-compat hints | ~350 | Entity 2023 |
| Hygon DCU Z100 | 7 | ~100 | 64GB HBM2 | ~1.0 | PCIe 5.0 | DTK (ROCm fork) | ~350 | Entity 2019 |
| Baidu Kunlun P800 | 7 (SMIC N+2) | ~345 | 64GB HBM2e | ~1.6 | XPU-Link | PaddlePaddle native | ~400 | Co. not listed |
| Iluvatar BI-V150 | 7 (TSMC) | ~147 | 32GB HBM2 | ~1.2 | PCIe 4.0 | Iluvatar SDK | ~300 | Monitored |
Dense peak TFLOPS vendor-published except where "~" marks AZR estimate. Real-world training throughput typically 40–65% of peak due to memory-bandwidth and interconnect bottlenecks. Chinese chips lose disproportionately here because of HBM supply constraints.
Sources: Cambricon 2024 annual report (SSE), SCMP, China Money Network.
Sources: Reuters, Bloomberg, Tom's Hardware.
Sources: SCMP Dec-2025, Tom's Hardware.
| Stack | Vendor | Target HW | Framework support | CUDA-compat? | Maturity |
|---|---|---|---|---|---|
| CUDA + cuDNN + TRT | NVIDIA | All NVIDIA GPUs | All | native | Mature · 18+ years |
| CANN + MindSpore | Huawei | Ascend 910/310 | MindSpore · PyTorch bridge (2024) · TF | Partial via torch-npu | Production · growing |
| BANG SDK / Neuware | Cambricon | MLU270/370/590 | PyTorch, TF plugins | Translation layer | Production |
| BIRENSUPA | Biren | BR100/104 | PyTorch (emerging) | HGAI translator | Early |
| MUSA | Moore Threads | MTT line | PyTorch, TF, DeepSpeed | MUSIFY translator | Early · expanding post-IPO |
| DTK (ROCm fork) | Hygon | DCU Z100 | PyTorch, TF via HIP | Indirect (HIP) | HPC-proven |
| PaddlePaddle | Baidu | Kunlun + multi-vendor | Native framework | Framework-level | Mature (China) |
| OneFlow / SiliconFlow | SiliconFlow (former OneFlow) | Vendor-agnostic | Custom + Python API | n/a | Research-grade |
| Triton (OpenAI) | Open-source | NVIDIA, AMD, emerging China | Python DSL → LLVM | CUDA kernel bypass | Rapidly adopted 2024-26 |
| SGLang + vLLM | Community (UCB et al.) | Multi-backend incl. Ascend/MLU | LLM serving | Abstracts backend | Dominant serving runtime |
The pattern of 2024–2026: rather than replace CUDA, the Chinese ecosystem has been abstracting above it. PyTorch 2.x's compiler stack (torch.compile + Triton) lets models target multiple hardware backends via an intermediate representation. SGLang and vLLM dominate LLM inference serving and support Ascend / MLU natively. The "software moat" is shallower than in 2020–2022 — but very real for custom kernels (FlashAttention variants, fused ops) where NVIDIA's ecosystem has years of hand-optimised lead.
Critically, DeepSeek V3 & R1 reportedly trained partially on Ascend 910B clusters and achieved frontier results — proof that the software gap, while real, is no longer fatal for well-funded research groups willing to absorb 20–40% efficiency penalties.
The China Integrated Circuit Industry Investment Fund Phase III (大基金三期) was registered 24 May 2024 with ¥344 billion ($47.5B) — larger than Phase I and II combined. Lead investors include the Ministry of Finance (¥60B), China Development Bank Capital, ICBC, Bank of China, Agricultural Bank of China, CCB, and Bank of Communications. Stated priorities:
Secondary channels: provincial government guidance funds (Shanghai, Shenzhen, Guangzhou, Anhui, Hubei) each run ¥50–200B vehicles that co-invest alongside the national fund. Cambricon, Biren and YMTC have each received direct subsidies and priority procurement from MIIT contracts.
The Dec 2023 Intel/AMD CPU ban for government PCs (SOEs to transition to Chinese hardware by 2027) is the most explicit demand-side intervention: it creates a guaranteed domestic market floor, independent of competitiveness on price or performance.
Sources: Reuters 27-May-2024; State Council & MoF filings.
| Foundry | HQ | Leading node | Cap (Kwpm) | Revenue ($B, 2024) | Key AI-chip customers | Sanction |
|---|---|---|---|---|---|---|
| SMIC (中芯国际) | Shanghai | 7nm (N+2 DUV) | ~850 | ~8.0 | Huawei HiSilicon, Hygon, Baidu Kunlun, Moore Threads (transition) | Entity 2020 |
| Hua Hong (华虹) | Shanghai/Wuxi | 28nm (pilot 22nm) | ~410 | ~2.0 | Power IC, MCU, limited AI inference | Not listed |
| Nexchip (合肥晶合) | Hefei | 28nm | ~120 | ~1.2 | Display drivers, CIS | Unsanctioned |
| CXMT (IDM) | Hefei | 17nm DRAM | ~240 | ~4.5 est. | In-house DRAM | Monitored |
| YMTC (IDM) | Wuhan | Xtacking 3.0 | ~100 | ~3.5 est. | In-house NAND | Entity 2022 |
| Wingtech / Nexperia | Shanghai/NL | Power/analog | ~60 (CN) | ~2.2 | Power management for AI servers | Monitored |
| TSMC Nanjing | Nanjing | 16/28nm (capped) | ~60 | n/d | Legacy AI inference | License-capped |
SMIC's 7nm (N+2) reality check: achieved via multi-patterned DUV immersion (ASML 1980i), confirmed in the Huawei Kirin 9000S (Aug 2023) and Ascend 910B/C. Yields widely reported at 20–30% vs TSMC's ~70% at equivalent node — 2–3× effective cost per good die. Each wafer runs through multiple patterning steps, consuming more equipment-hours, so real 7nm AI-chip capacity is closer to 30–50K wpm, not the 100K+ headline number. That is the binding supply constraint on Ascend 910C shipments in 2025–2026.
| Company | P(global top-5) | P(NVIDIA parity <5y) | Gov support | Dominant risk |
|---|---|---|---|---|
| Huawei HiSilicon | 5 / 5 | HBM supply + SMIC yield ceiling | ||
| Cambricon | 5 / 5 | Customer concentration, R&D burn | ||
| Biren | 4 / 5 | Fab access, software stack immaturity | ||
| Moore Threads | 3 / 5 | Structurally trailing node (12nm) | ||
| Hygon | 4 / 5 | AMD IP ageing out of relevance | ||
| Horizon Robotics (edge) | 3 / 5 | Not a training-chip competitor | ||
| YMTC (NAND) | 5 / 5 | Equipment access, yield | ||
| CXMT (DRAM/HBM) | 5 / 5 | HBM stacking IP, EUV cutoff | ||
| Baidu Kunlun | 3 / 5 | Captive customer = ceiling | ||
| Alibaba T-Head | 3 / 5 | Internal use only, strategic focus shifts | ||
| Iluvatar CoreX | 3 / 5 | Scale, ecosystem | ||
| Enflame (Suiyuan) | 3 / 5 | Tencent captive, differentiation | ||
| MetaX | 3 / 5 | Late entrant, funding |
These are author estimates synthesised from revenue trajectory, fab access, software maturity, customer diversity, and policy support. "P(global top-5)" means: share of forecasts where the company appears in global AI-chip revenue top-5 by 2030. "P(NVIDIA parity)" means: share of forecasts where effective training throughput per dollar matches NVIDIA's contemporary flagship within 5 years. Inherent model uncertainty: ±15 pp.
| Company | Bull case (2028) | Bear case (2028) |
|---|---|---|
| Huawei | CloudMatrix 384 becomes de-facto China training standard; Ascend 920 on SMIC N+3 reaches 80%+ H100-next parity; exports to Belt-and-Road; $25B+ AI revenue. | HBM stockpile exhausts 2027; SMIC yield stays stuck <30%; CANN ecosystem fragmented; market reverts to stockpiled H20s; $8B AI revenue. |
| Cambricon | MLU690 ships on SMIC N+2 at ~70% H100; sustained profitability; ¥5B revenue run-rate; second curve M&A into edge. | Government mandates drop; Huawei absorbs demand; returns to losses; stock retraces below IPO price. |
| Biren | BR200 on SMIC 7nm ships 2026; HK-listed stock re-rates on profitability; China Telecom/Mobile become anchor customers. | BR200 delays; co-founders continue departing; IPO capital depletes; acquired by Huawei or Tencent at distressed price. |
| Moore Threads | MUSA matures into credible CUDA alternative for serving; dominant domestic gaming GPU; KUAE finds niche in inference clusters. | Consumer GPU margins collapse under Lisuan/Innosilicon; enterprise AI ambitions fail; post-IPO drift. |
| Hygon | x86 government-PC mandate drives 40% revenue CAGR; DCU finds HPC supercomputing niche; JV profit hits ¥10B. | Intel/AMD regain access via negotiation; Loongson/LoongArch take domestic CPU share; x86 Chinese franchise stagnates. |
| Horizon Robotics | Journey 7 wins tier-1 European OEM; becomes #1 global ADAS chip by volume (past Mobileye); ¥15B revenue. | NEV demand slows; Xiaomi/Nio/Xpeng insource; VW JV underperforms; growth decelerates to single digits. |
| YMTC | 300+ layer NAND ships 2026; 10%+ global share; Apple/HP enterprise wins; becomes 4th global NAND maker. | Yield issues persist; US extends NAND controls directly; stuck at ~5% share, operational losses return. |
| CXMT | HBM2e volume production late 2026; feeds Ascend/MLU clusters; 15% global DRAM by 2028; first Chinese HBM exporter. | Added to full Entity List; EUV denied; HBM project stalls at pilot; stays commodity-DRAM-only. |
| Hyperscaler | NVIDIA stockpile (est.) | Primary Chinese AI chip | Secondary | Foundation model |
|---|---|---|---|---|
| Baidu (AI Cloud, Apollo) | Pre-Oct 2022 A100s + H20s | Kunlun P800 (own) | Ascend 910B | ERNIE 4.5 / 5.0 |
| Alibaba (Aliyun) | Large A800/H800 + H20 | T-Head Hanguang 800 (inference) | Ascend 910C, H20 | Qwen 3 / Qwen-VL |
| Tencent | H20 + legacy H800 | Enflame CloudBlazer | Ascend 910B, internal XPU | Hunyuan |
| ByteDance | H100/H200 (pre-ban + third-party) + H20 | In-house ASIC (2024-25) | Ascend 910B/C | Doubao, Seed-LLM |
| Huawei Cloud | Limited NVIDIA — mostly domestic | Ascend 910B/C (own) | Cambricon MLU590 | Pangu 5.0 |
| DeepSeek / High-Flyer | Documented H800 & H100 pre-ban clusters | Ascend 910B (reported) | Mixed NVIDIA + Ascend | DeepSeek V3, R1 |
| Moonshot / 01.ai | H800 stockpile | Mixed NVIDIA + Ascend | — | Kimi, Yi |
| China Mobile Cloud | H20 + limited H800 | Ascend 910C | MLU590, Biren BR100 pilots | Jiutian |
| China Telecom Cloud | H20 | Ascend 910C | Biren BR100 (intelligent compute centres) | TeleChat |
| iFlytek | Legacy | Ascend 910B/C (heavy) | Cambricon MLU590 | Spark 4.0 |
The headline pattern: Huawei Ascend is the default, NVIDIA H20 is the premium. Pre-2023 H100/H800 stockpiles are the rarest and most valuable — reserved for frontier training runs at ByteDance, Alibaba, DeepSeek. Everything else (inference, fine-tuning, enterprise serving) is migrating to domestic silicon at pace, driven partly by price-performance and partly by state-owned enterprise procurement rules.
Where a vendor published a figure (peak TFLOPS, TDP, memory bandwidth), it is reported as-is. "Effective vs H100" percentages are AZR synthesis based on benchmark reports from users (MLPerf, Stanford AI Index, informal DeepSeek / Alibaba training comms), weighted toward memory-bandwidth-limited workloads (LLM training) rather than peak-TFLOPS-limited (dense convolution).
Probability scores are subjective point estimates from a single analyst (this author) with no formal calibration. Treat as directional, not precise. Methodology: for each company, score on (1) technical trajectory, (2) fab/supply access, (3) software ecosystem, (4) customer diversity, (5) financial runway, (6) political backing — then combine via rough weights. Error bars ±15 percentage points.
Revenue figures where not disclosed are marked "est." or "n/d". HBM "pilot" status reflects public reports as of 2026-Q1; pilot does not imply volume production.
All financial conversions use USD/CNY ≈ 7.25 unless otherwise noted.
v1.0 · 2026-05-05 — Initial release. Compiled by AZR (digital scientist) for Alex.
Refresh cadence: quarterly, or on major policy events.